The subject invention is directed generally to test circuitry for integrated circuits, and more particularly to test circuitry that allows for electrical testing on input and/or output (I/O) circuits of integrated circuits without physically contacting each of the externally accessible I/O contact pads of the I/O circuits.
Integrated circuits include input circuits for receiving a input signals, and output circuits for delivering output signals. An input circuit is commonly implemented by an input buffer, while an output circuit is commonly implemented by an output driver. The inputs to input circuits such as input buffers are typically connected to associated contact pads, while the outputs of output circuits such as output drivers are connected to associated contact pads. An input circuit and an output circuit are sometimes combined to provide a bidirectional input/output (I/O) circuit wherein a single contact pad is connected to the input of the input circuit and to the output of the output circuit. For ease of reference, input circuits, output circuits, and bidirectional I/O circuits shall herein be called inputs, outputs, and bidirectional I/Os, respectively, and as I/O circuits or I/Os collectively. Also for ease of reference, the contact pads associated with the inputs, outputs, and bidirectional I/Os shall be called I/O contact pads, since input circuits, output circuits and bidirectional I/O circuits are connected to associated pads.
Integrated circuits are commonly tested with automatic test equipment (ATE) which typically provide respective probes for I/O contact pads of the integrated circuit being tested. Important considerations with known ATE testing include the possibility of probe damage to the I/O contact pads, complexity of test fixturing that must allow for all I/O contact pads to be directly contacted, limitations imposed on the number of I/O circuits due to the ATE capabilities as to the maximum number of I/O contact pads that can be contacted, and ATE cost which is a direct function of the number of I/O pads to be contacted.
There are a number of techniques available to test the interior logic of digital IC's without contacting all the I/O pads. These include scan techniques by which tests are loaded and evaluated serially, and Built-in Self-Test (BIST) in which the chip tests itself on command. While these techniques can fully test the interior of a chip while using just a few I/O circuits, the remaining I/O circuits are not tested for DC electrical parameters such as the voltage and current drive characteristics of the outputs circuits, the logic threshold voltages of the input circuits, the leakage current of input circuits, and the leakage current of output circuits in the high impedance state.
The testing of I/O circuit DC electrical parameters has heretofore required direct probing from ATE of the I/O circuits. The invention provides a means of testing the electrical parameters of I/O without direct probing, and when used in addition to the aforementioned techniques, allows an integrated circuit to be fully tested by contacting only a few of the many possible I/O pads.